1. Field
Embodiments of the present invention relate to a delay locked loop, and more particularly, to a multi-channel delay locked loop that includes a global delay locked loop and a plurality of local delay locked loops in order to reduce power consumption while improving a locking speed.
2. Description of the Related Art
In high-speed interfaces such as universal serial bus (USB), peripheral component interconnect express (PCI) Express, and model driven message interoperability (MDMI), as well as memory interface circuits such as a double data rate (DDR) memory interface circuit and a low power double data rate (LPDDR) memory interface circuit, a plurality of channels are generally used to transmit a clock signal or data. Conventionally, an independent delay locked loop has been used for each channel, in order to perform a locking operation.
FIG. 1 is a block diagram illustrating a conventional multi-channel delay locked loop 10.
The conventional multi-channel delay locked loop 10 may include a plurality of delay locked loops (DLLs) 11 which independently operate.
The delay locked loops 11 lock delays between an input clock signal CLKIN and output clock signals CLKOUT1, CLKOUT2, . . . , and CLKOUTN, respectively.
FIG. 2 is a block diagram illustrating the delay locked loop 11 of FIG. 1.
The delay locked loop 11 may include a variable delay line 1, a delay model 2, a phase comparator 3, and a delay line controller 4.
The variable delay line 1 adjusts a delay amount of the input clock signal CLKIN according to a delay control signal DCODE, and outputs the output clock signal, e.g., CLKOUT1. Since the variable delay line 1 may use a well-known variable delay line that adjusts a delay amount according to a delay control signal, detailed descriptions of the variable delay line 1 are omitted herein.
The delay model 2 delays the output clock signal CLKOUT1 by a modeled time, and outputs a feedback clock signal CLKFB. If the input clock signal CLKIN and the output clock signal CLKOUT1 are intended to be set in phase, the delay model 2 may not be required.
The phase comparator 3 compares a phase of the input clock signal CLKIN and a phase of the feedback clock signal CLKFB, and outputs a phase difference signal PD representing a difference between the phase of the input clock signal CLKIN and the phase of the feedback clock signal CLKFB.
The delay line controller 4 outputs the delay control signal DCODE according to the phase difference signal PD.
The delay locked loop 11 constantly locks a delay between the input clock signal CLKIN and the output clock signal CLKOUT1 through the feedback control.
Since the conventional multi-channel delay locked loop 10 includes the plurality of delay locked loops 11 which independently operate for the respective channels, a circuit area and power consumption of the loop 10 are inevitably increased. Furthermore, the multi-channel delay locked loop 10 may require a relatively long time until all of the channels are locked.